8. 修改Uboot开机logo

8.1. 简介

开机LOGO即是上电LOGO，因为UBOOT的启动时间较短显示的LOGO存在时间也较短，现在大部分使用的是Linux内核启动Logo，但为了教程的严谨性，我还是讲解一下Uboot的开机LOGO。

如需更实用的参考本教程下面的章节 修改Linux内核启动Logo

由于NXP官方在近几年的Uboot版本不提供LOGO显示功能，所以需要自己配置LCD引脚和驱动，由于找遍全网也没详细的教程，以下内容为本人摸索得出，如有错误欢迎指正。

8.2. 下载安装编译镜像系统

使用平台：Ubuntu 18.04.5 LTS 版本

可以使用我们提供的虚拟机镜像 https://doc.embedfire.com/products/link/zh/latest/linux/ebf_i.mx6ull.html#id4

也可以自己下载ubuntu 18.04.5 LTS官方镜像搭建

https://mirrors.aliyun.com/ubuntu-releases/bionic/ubuntu-18.04.5-desktop-amd64.iso

8.3. 安装编译工具和依赖

使用apt工具能快速安装好我们需要的工具和依赖

  sudo apt install make git gcc-arm-none-eabi gcc bison flex libssl-dev dpkg-dev lzop libncurses5-dev

8.4. 下载Uboot源代码

可以到我们的gitee上下载我们的源码，也可以下载NXP官方的源码进行配置，本教程就以我们野火修改过的Uboot进行讲解

我们的UBOOT地址：https://gitee.com/Embedfire/ebf_linux_uboot/tree/ebf_v2020_10_imx/

NXP官方的UBOOT地址：https://source.codeaurora.org/external/imx/uboot-imx/

  #获取野火uboot
  git clone -b ebf_v2020_10_imx https://gitee.com/Embedfire/ebf_linux_uboot

  #或者
  git clone -b ebf_v2020_10_imx https://github.com/Embedfire/ebf_linux_uboot

8.5. 文件配置

8.5.1. 头文件

文件位置：include/configs/mx6ullfire.h

在该文件的末尾的endif前添加如下代码

      #define CONFIG_VIDEO_MXS
      #define CONFIG_VIDEO_LOGO
      #define CONFIG_SPLASH_SCREEN
      #define CONFIG_SPLASH_SCREEN_ALIGN
      #define CONFIG_VIDEO_BMP_LOGO
      #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR

CONFIG_VIDEO_MXS：定义了LCD的引脚和初始化

CONFIG_VIDEO_LOGO：定义了video_logo的一些封装函数

CONFIG_SPLASH_SCREEN：定义了LCD的初始化函数

CONFIG_SPLASH_SCREEN_ALIGN：定义了和屏幕对齐的函数

CONFIG_VIDEO_BMP_LOGO：定义了BMP文件格式支持函数

MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR：定义了LCD的基地址：0x021C8000

8.5.2. 配置文件

根据自己的板型选择设置

EMMC的配置文件（包含SD卡）：/root/uboot/mx6ull_fire_mmc_defconfig

nand的配置文件：/root/uboot/mx6ull_fire_nand_defconfig

在文件末尾加上

  CONFIG_CMD_BMP=y
  CONFIG_VIDEO=y

CONFIG_CMD_BMP：使能了BMP调用命令

CONFIG_VIDEO：开启VIDEO功能

8.5.3. 单板文件

文件位置：board/freescale/mx6ullfire/mx6ullfire.c

该文件添加的内容较多，具体详看代码

若代码复制不方面可以直接下载源码文件进行替换 mx6ullfire.c

其中以//—-1–开头，以//—-2–结尾则为添加的内容

  #include <init.h>
  #include <linux/delay.h>
  #include <asm/arch/clock.h>
  #include <asm/arch/iomux.h>
  #include <asm/arch/imx-regs.h>
  #include <asm/arch/crm_regs.h>
  #include <asm/arch/mx6-pins.h>
  #include <asm/arch/sys_proto.h>
  #include <asm/gpio.h>
  #include <asm/mach-imx/iomux-v3.h>
  #include <asm/mach-imx/boot_mode.h>
  #include <asm/io.h>
  #include <common.h>
  #include <env.h>
  #include <fsl_esdhc_imx.h>
  #include <linux/sizes.h>
  #include <mmc.h>
  #include <miiphy.h>
  #include <stdio.h>
  #include <configs/mx6ullfire.h>
  #include <stdlib.h>

  //---------------------------------------------------111-----------
  //---------------------------------------------------111-----------
  //---------------------------------------------------111-----------
  #include <asm/arch/mx6ull_pins.h>
  #include <asm/mach-imx/mxc_i2c.h>
  #include <i2c.h>
  #include <netdev.h>
  #include <power/pmic.h>
  #include <power/pfuze3000_pmic.h>
  #include <usb.h>
  #include <usb/ehci-ci.h>
  //-----------------------------------------------------222-------------
  //-----------------------------------------------------222-------------
  //-----------------------------------------------------222-------------


  //#include <stdlib.h>

  //------------------------------------------------------------
  //时钟控制寄存器
  int *CCM_CCGR2_my=(int *)0x20C4070;
  //LCD_DATA11(GPIO3_16)复用功能选择寄存器
  int *IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_my=(int *)0x20E0144;
  //PAD属性设置寄存器
  int *IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_my=(int *)0x20E03D0;
  //GPIO3方向设置寄存器
  int *GPIO3_GDIR_my=(int *)0x20A4004;
  //GPIO输出状态寄存器
  int *GPIO3_DR_my=(int *)0x20A4000;
  //GPIO输入状态寄存器
  int *GPIO3_PSR_my=(int *)0x20A4008;
  int LCD_DATA11_FLAG_my=-1;
  //------------------------------------------------------------


  int lcdreset=0;


  DECLARE_GLOBAL_DATA_PTR;

  #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |         \
    PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |         \
    PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

  #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
        PAD_CTL_SRE_FAST)
  #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)

  //------------------------------------------1111111111111
  #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
    PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)

  #define IOX_SDI IMX_GPIO_NR(5, 10)
  #define IOX_STCP IMX_GPIO_NR(5, 7)
  #define IOX_SHCP IMX_GPIO_NR(5, 11)
  #define IOX_OE IMX_GPIO_NR(5, 8)

  static iomux_v3_cfg_t const iox_pads[] = {
    /* IOX_SDI */
    MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
    /* IOX_SHCP */
    MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
    /* IOX_STCP */
    MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
    /* IOX_nOE */
    MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };


  /*
  * HDMI_nRST --> Q0
  * ENET1_nRST --> Q1
  * ENET2_nRST --> Q2
  * CAN1_2_STBY --> Q3
  * BT_nPWD --> Q4
  * CSI_RST --> Q5
  * CSI_PWDN --> Q6
  * LCD_nPWREN --> Q7
  */
  enum qn {
    HDMI_NRST,
    ENET1_NRST,
    ENET2_NRST,
    CAN1_2_STBY,
    BT_NPWD,
    CSI_RST,
    CSI_PWDN,
    LCD_NPWREN,
  };

  enum qn_func {
    qn_reset,
    qn_enable,
    qn_disable,
  };

  enum qn_level {
    qn_low = 0,
    qn_high = 1,
  };

  static enum qn_level seq[3][2] = {
    {0, 1}, {1, 1}, {0, 0}
  };

  static enum qn_func qn_output[8] = {
    qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
    qn_disable, qn_disable
  };

  static void iox74lv_init(void)
  {
    int i;

    gpio_direction_output(IOX_OE, 0);

    for (i = 7; i >= 0; i--) {
      gpio_direction_output(IOX_SHCP, 0);
      gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
      udelay(500);
      gpio_direction_output(IOX_SHCP, 1);
      udelay(500);
    }

    gpio_direction_output(IOX_STCP, 0);
    udelay(500);
    /*
    * shift register will be output to pins
    */
    gpio_direction_output(IOX_STCP, 1);

    for (i = 7; i >= 0; i--) {
      gpio_direction_output(IOX_SHCP, 0);
      gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
      udelay(500);
      gpio_direction_output(IOX_SHCP, 1);
      udelay(500);
    }
    gpio_direction_output(IOX_STCP, 0);
    udelay(500);
    /*
    * shift register will be output to pins
    */
    gpio_direction_output(IOX_STCP, 1);
  };
  //------------------------------------2222222



  int dram_init(void)
  {
    gd->ram_size = imx_ddr_size();

    return 0;
  }

  static iomux_v3_cfg_t const uart1_pads[] = {
    MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
    MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };

  static void setup_iomux_uart(void)
  {
    imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  }

  int board_mmc_get_env_dev(int devno)
  {
    return devno;
  }

  int mmc_map_to_kernel_blk(int devno)
  {
    return devno;
  }

  int board_early_init_f(void)
  {
    setup_iomux_uart();

    return 0;
  }

  #ifdef CONFIG_NAND_MXS
  static iomux_v3_cfg_t const nand_pads[] = {
    MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
    MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  };

  static void setup_gpmi_nand(void)
  {
    struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

    /* config gpmi nand iomux */
    imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));

    /* enable apbh clock gating */
    setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  }
  #endif

  #ifdef CONFIG_FEC_MXC
  static int setup_fec(int fec_id)
  {
    struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
    int ret;

    if (fec_id == 0) {
      /*
      * Use 50MHz anatop loopback REF_CLK1 for ENET1,
      * clear gpr1[13], set gpr1[17].
      */
      clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
          IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
    } else {
      /*
      * Use 50MHz anatop loopback REF_CLK2 for ENET2,
      * clear gpr1[14], set gpr1[18].
      */
      clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
          IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
    }

    ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
    if (ret)
      return ret;

    enable_enet_clk(1);

    return 0;
  }

  int board_phy_config(struct phy_device *phydev)
  {
    phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);

    if (phydev->drv->config)
      phydev->drv->config(phydev);

    return 0;
  }
  #endif




  /*-------------------------------------------111--------------------------------------------------*/
  /*-------------------------------------------111--------------------------------------------------*/
  /*--------------------------------------------1111-------------------------------------------------*/
  /*---------------------------------------------111------------------------------------------------*/
  /*---------------------------------------------111------------------------------------------------*/



  #ifdef CONFIG_VIDEO_MXS
  static iomux_v3_cfg_t const lcd_pads[] = {
    MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
    MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

    /* LCD_RST */
    MX6_PAD_LCD_RESET__LCDIF_RESET | MUX_PAD_CTRL(NO_PAD_CTRL),

    /* Use GPIO for Brightness adjustment, duty cycle = period. */
    MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };

  static int setup_lcd(void)
  {
    enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);

    imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

    /* Reset the LCD */
    gpio_request(IMX_GPIO_NR(3, 4), "lhf1");
    gpio_request(IMX_GPIO_NR(1, 8), "lhf2");

    gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
    udelay(500);
    gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);

    /* Set Brightness to high */
    gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
    printf("LCD_UP\r\n");
    return 0;
  }
  #endif





  /*-----------------------------------------222----------------------------------------------------*/
  /*----------------------------------------222-----------------------------------------------------*/
  /*-----------------------------------------22----------------------------------------------------*/
  /*-----------------------------------------222----------------------------------------------------*/
  /*-----------------------------------------222----------------------------------------------------*/










  int board_init(void)
  {
    *(CCM_CCGR2_my)=0xFFFFFFFF;
    *(IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_my)=0x05;
    *(IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_my)=0x100B0;
    *(GPIO3_GDIR_my)&=~(1<<16);
    *(GPIO3_DR_my)|=1<<16;

    /* Address of boot parameters */
    gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;


  #ifdef      CONFIG_FEC_MXC
    setup_fec(CONFIG_FEC_ENET_DEV);
  #endif

  #ifdef CONFIG_NAND_MXS
    setup_gpmi_nand();
  #endif


  /*----------------------------------------111-----------------------------------------------------*/
  /*------------------------------------------111---------------------------------------------------*/
  /*-----------------------------------------111----------------------------------------------------*/
  /*---------------------------------------------------------------------------------------------*/

    imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));

    //iox74lv_init();



  #ifdef CONFIG_VIDEO_MXS
    setup_lcd();
  #endif


  /*----------------------------------------2222-----------------------------------------------------*/
  /*----------------------------------------222-----------------------------------------------------*/
  /*----------------------------------------222-----------------------------------------------------*/
  /*----------------------------------------2222-----------------------------------------------------*/




    return 0;
  }

  #ifdef CONFIG_CMD_BMODE
  static const struct boot_mode board_boot_modes[] = {
    /* 4 bit bus width */
    {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
    {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
    {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
    {NULL,     0},
  };
  #endif

  int board_late_init(void)
  {

    mdelay(500);
    LCD_DATA11_FLAG_my=*(GPIO3_DR_my)>>16&1;
    gpio_request(IMX_GPIO_NR(3, 10), "sd0");
    gpio_direction_input(IMX_GPIO_NR(3, 10));
    lcdreset = gpio_get_value(IMX_GPIO_NR(3, 10));

    if(lcdreset||LCD_DATA11_FLAG_my)
    {
      env_set("bootcmd_mmc0","lhf");
      //printf("\n\npao le emmc\n\n");
    }
    else
    {
      env_set("bootcmd_mmc0","setenv devtype mmc; setenv mmcdev 0; setenv bootpart 0:1 ; setenv rootfpart 0:2 ; run boot");
      //printf("\n\npao le sd \n\n");
    }



  #ifdef CONFIG_CMD_BMODE
    add_board_boot_modes(board_boot_modes);
  #endif

  #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
    if (is_cpu_type(MXC_CPU_MX6ULZ))
      env_set("board_name", "ULZ-EVK");
    else
      env_set("board_name", "EVK");
    env_set("board_rev", "14X14");
  #endif




    return 0;
  }

  int checkboard(void)
  {
    if (is_cpu_type(MXC_CPU_MX6ULZ))
      puts("Board: MX6ULZ 14x14 EVK\n");
    else
      puts("Board: MX6ULL 14x14 EVK\n");

    return 0;
  }

8.5.4. 添加LOGO和配置Makefile

添加LOGO目录：tools/logos

  LOGO要求：
        格式：bmp
        色深：8
        大小：100KB以下

如果手上没有符合要求的LOGO图，可以先使用logos中的图，也可以下载该图使用 ebf.bmp

将下载好的文件添加到 tools/logos

Makefile文件位置：tools/Makefile

   LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
   改为
   LOGO_BMP= $(srctree)/$(src)/logos/ebf.bmp

8.6. 编译

  make distclean
  make mx6ull_fire_mmc_defconfig CROSS_COMPILE=arm-none-eabi-
  #编译uboot
  make CROSS_COMPILE=arm-none-eabi- -j4

8.7. 烧录启动